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LTC1344A Software-Selectable Cable Terminator
FEATURES
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DESCRIPTION
The LTC (R)1344A features six software-selectable multiprotocol cable terminators. Each terminator can be configured as an RS422 (V.11) 100 minimum differential load, V.35 T-network load or an open circuit for use with RS232 (V.28) or RS423 (V.10) transceivers that provide their own termination. When combined with the LTC1543 and LTC1544, the LTC1344A forms a complete software-selectable multiprotocol serial port. A data bus latch feature allows sharing of the select lines between multiple interface ports. The LTC1344A is similar to the LTC1344 except for a difference in the Mode Selection table. The LTC1344A is available in a 24-lead SSOP.
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Software-Selectable Cable Termination for: RS232 (V.28) RS423 (V.10) RS422 (V.11) RS485 RS449 EIA530 EIA530-A V.35 V.36 X.21 Outputs Won't Load the Line with Power Off
APPLICATIONS
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Data Networking CSU and DSU Data Routers
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATION
DTE or DCE Multiprotocol Serial Interface with DB-25 Connector
LL CTS DSR DCD DTR RTS RXD RXC TXC SCTE TXD
Daisy-Chained Control Outputs
LTC1544 D4 R4 R3 R2 R1 D3 D2 D1 R3 R2 R1
LTC1543 D3 D2 D1
18 LL A (141)
13 5 CTS B CTS A (106)
10 8 DSR B DSR A (109)
22 6 DCD B DCD A (107)
23 20 19 4 DTR B DTR A (108) RTS B RTS A (105) SHIELD (101)
1 SG (102)
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16 3 RXD B RXD A (104)
9 RXC B
17 RXC A (115)
12 15 11 24 14 SCTE B SCTE A (113) TXD B TXD A (103) TXC B TXC A (114)
DB-25 CONNECTOR
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LTC1344A
2
1344A TA01
1
LTC1344A ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER I FOR ATIO
TOP VIEW M0 VEE R1C R1B R1A R2A R2B R2C R3A 1 2 3 4 5 6 7 8 9 24 M1 23 M2 22 DCE/DTE 21 LATCH 20 R6B 19 R6A 18 R5A 17 R5B 16 R4A 15 R4B 14 VCC 13 GND
Positive Supply Voltage (VCC) ................................... 7V Negative Supply Voltage (VEE) ........................... - 13.2V Input Voltage (Logic Inputs) .................... (VEE - 0.3V) to (VCC + 0.3V) Input Voltage (Load Inputs) .................................. 18V Power Dissipation .............................................. 600mW Operating Temperature Range LTC1344AC ............................................ 0C to 70C LTC1344AI ......................................... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
ORDER PART NUMBER LTC1344ACG LTC1344AIG
R3B 10 R3C 11 GND 12
G PACKAGE 24-LEAD PLASTIC SSOP TJMAX = 150C, JA = 100C/W
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
VCC = 5V 5%, VEE = - 5V 5%, TA = TMIN to TMAX (Notes 2, 3) unless otherwise noted.
SYMBOL Supplies ICC RV.35 Supply Current Differential Mode Impedance Common Mode Impedance All Digital Pins = GND or VCC All Loads (Figure 1), - 2V VCM 2V (Commercial) All Loads (Figure 2), - 2V VCM 2V (Commercial) All Loads (Figure 1), - 2V VCM 2V (Industrial) All Loads (Figure 2), - 2V VCM 2V (Industrial) RV.11 Differential Mode Impedance All Loads (Figure 1), VCM = 0V (Commercial) All Loads (Figure 1), - 7V VCM 7V (Commercial) All Loads (Figure 1), VCM = 0V (Industrial) All Loads (Figure 1), - 7V VCM 7V (Industrial) ILEAK VIH VIL IIN High Impedance Leakage Current Input High Voltage Input Low Voltage Input Current All Loads, - 7V VCM 7V All Logic Input Pins All Logic Input Pins All Logic Input Pins Logic Inputs
q q q q
PARAMETER
CONDITIONS
MIN
TYP 0.4
MAX 1.0 110 165 115 170 110 115 50
UNITS mA A V
Terminator Pins
q q q q q q q
90 135 90 130 100 100 95 100
104 153 104 153 104 104 104 104 1
2 0.8 10
The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are reference to ground unless otherwise specified. Note 3: All typicals are given at VCC = 5V, VEE = - 5V, TA = 25C.
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LTC1344A TYPICAL PERFORMANCE CHARACTERISTICS
V.11 or V.35 Differential Mode Impedance vs Temperature
120 DIFFERENTIAL MODE IMPEDANCE () DIFFERENTIAL MODE IMPEDANCE ()
108
115
VCM = -7V
106
110
VCM = -2V VCM = 0V
DIFFERENTIAL MODE IMPEDANCE ()
105 VCM = 7V 100 -40 -20 0 20 40 60 80 100
1344 G01
TEMPERATURE (C)
V.11 or V.35 Differential Mode Impedance vs Negative Supply Voltage (VEE)
105 165 TA = 25C COMMON MODE IMPEDANCE () 160
DIFFERENTIAL MODE IMPEDANCE ()
COMMON MODE IMPEDANCE ()
104
103 - 5.4 - 5.2 - 5.0 - 4.8 VEE VOLTAGE (V) - 4.6
1344 G04
V.35 Common Mode Impedance vs Supply Voltage (VCC)
153 TA = 25C 154
COMMON MODE IMPEDANCE ()
COMMON MODE IMPEDANCE ()
SUPPLY CURRENT (A)
152
151 4.6 4.8 5.0 5.2 VCC VOLTAGE (V) 5.4
1344 G07
UW
V.11 or V.35 Differential Mode Impedance vs Common Mode Voltage
105 TA = 25C
V.11 or V.35 Differential Mode Impedance vs Supply Voltage (VCC)
TA = 25C
104
104
102
100
103 -8 -6 - 4 -2 0 2 4 6 COMMON MODE VOLTAGE (V) 8 4.6 4.8 5.0 5.2 VCC VOLTAGE (V) 5.4
1344 G03
1344 G02
V.35 Common Mode Impedance vs Temperature
158
V.35 Common Mode Impedance vs Common Mode Voltage
TA = 25C 156
VCM = -2V 155
154
150 VCM = 2V 145 - 40 -20
VCM = 0V
152
0
60 40 20 TEMPERATURE (C)
80
100
1344 G05
150 -2
0 -1 1 COMMON MODE VOLTAGE (V)
2
1344 G06
V.35 Common Mode Inpedance vs Negative Supply Voltage (VEE)
500
TA = 25C
Supply Current vs Temperature
153
420
152
340
151
260
150
- 5.4
- 5.2 - 4.8 - 5.0 VEE VOLTAGE (V)
- 4.6
1344 G08
180 -40 -20
0
40 60 20 TEMPERATURE (C)
80
100
1344 G09
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LTC1344A
PIN FUNCTIONS
M0 (Pin 1): TTL Level Mode Select Input. The data on M0 is latched when LATCH is high. VEE (Pin 2): Negative Supply Voltage Input. Can connect directly to the LTC1543 VEE pin. Connect a 1F capacitor to ground. R1C (Pin 3): Load 1 Center Tap. R1B (Pin 4): Load 1 Node B. R1A (Pin 5): Load 1 Node A. R2A (Pin 6): Load 2 Node A. R2B (Pin 7): Load 2 Node B. R2C (Pin 8): Load 2 Center Tap. R3A (Pin 9): Load 3 Node A. R2B (Pin 10): Load 2 Node B. R3C (Pin 11): Load 3 Center Tap. GND (Pin 12): Ground Connection for Load 1 to Load 3. GND (Pin 13): Ground Connection for Load 4 to Load 6. VCC (Pin 14): Positive Supply Input. 4.75V VCC 5.25V. R4B (Pin 15): Load 4 Node B. R4A (Pin 16): Load 4 Node A. R5B (Pin 17): Load 5 Node B. R5A (Pin 18): Load 5 Node A. R6A (Pin 19): Load 6 Node A. R6B (Pin 20): Load 6 Node B. LATCH (Pin 21): TTL Level Logic Signal Latch Input. When LATCH is low the input buffers on M0, M1, M2 and DCE/ DTE are transparent. When LATCH is high the logic pins are latched into their respective input buffers. The data latch allows the select lines to be shared between multiple I/O ports. DCE/DTE (Pin 22): TTL Level Mode Select Input. DCE mode is selected when high and DTE mode when low. The data on DCE/DTE is latched when LATCH is high. M2 (Pin 23): TTL Level Mode Select Input 1. The data on M2 is latched when LATCH is high. M1 (Pin 24): TTL Level Mode Select Input 2. The data on M1 is latched when LATCH is high.
TEST CIRCUITS
C A R1 51.5 S1 ON S2 OFF R2 51.5 R3 124 LTC1344A
B V 7V OR 2V
1344 F01
Figure 1. Differential V.11 or V.35 Impedance Measurement
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C LTC1344A R1 51.5 S1 ON A, B R2 51.5 V 2V S2 ON R3 124
1344 F02
Figure 2. V.35 Common Mode Impedance Measurement
LTC1344A
ODE SELECTIO
X 0 1 0 1 0 1 0 1 0 1 X X LTC1344A MODE NAME V.10/RS423 RS530A RS530 X.21 V.35 RS449/V.36 V.28/RS232 No Cable
DCE/DTE
X = don't care, 0 = logic low, 1 = logic high
A R1 51.5 S1 ON S2 OFF R2 51.5 B
V.11 Mode
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M2 0 0 0 0 0 0 0 1 1 1 1 1 1 M1 0 0 0 1 1 1 1 0 0 0 0 1 1 M0 0 1 1 0 0 1 1 0 0 1 1 0 1 R1 Z Z Z Z Z Z Z V.35 V.35 Z Z Z V.11 R2 Z Z Z Z Z Z Z V.35 V.35 Z Z Z V.11 R3 Z Z Z Z Z Z Z Z V.35 Z Z Z V.11 R4 Z V.11 Z V.11 Z V.11 Z V.35 Z V.11 Z Z V.11 R5 Z V.11 V.11 V.11 V.11 V.11 V.11 V.35 V.35 V.11 V.11 Z V.11 R6 Z V.11 V.11 V.11 V.11 V.11 V.11 V.35 V.35 V.11 V.11 Z V.11
C LTC1344A A R1 51.5 S1 ON S2 ON R2 51.5 B B C LTC1344A A R1 51.5 S1 OFF S2 OFF R2 51.5 C LTC1344A R3 124 R3 124 R3 124
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V.35 Mode
High-Z Mode
1344 F03
Figure 3. LTC1344A Modes
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LTC1344A
APPLICATIONS INFORMATION
Multiprotocol Cable Termination One of the most difficult problems facing the designer of a multiprotocol serial interface is how to allow the transmitters and receivers for different electrical standards to share connector pins. In some cases the transmitters and receivers for each interface standard can be simply tied together and the appropriate circuitry enabled. But the biggest problem still remains: how to switch the various cable termination required by the different standards. Traditional implementations have included switching resistors with expensive relays or requiring the user to change termination modules every time the interface standard has changed. Custom cables have been used with the termination in the cable head. Another method uses separate termination built on the board, and a custom cable which routes the signals to the appropriate termination. Switching the termination using FETs is difficult because the FETs must remain off even though the signal voltage is beyond the supply voltage for the FET drivers or the power is off.
Z
The LTC1344A solves the cable termination switching problem via software control. The LTC1344A provides termination for the V.10 (RS423), V.11 (RS422), V.28 (RS232) and V.35 electrical protocols. V.10 (RS423) Termination A typical V.10 unbalanced interface is shown in Figure 4. A V.10 single-ended generator output A with ground C is connected to a differential receiver with input A' connected to A and input C' connected to the signal return ground C. Usually no cable termination is required for V.10 interfaces but the receiver inputs must be compliant with the impedance curve shown in Figure 5. In V.10 mode, both switches S1 and S2 are turned off so the only cable termination is the input impedance of the V.10 receiver.
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GENERATOR
BALANCED INTERCONNECTING CABLE
LOAD CABLE TERMINATION RECEIVER
A C
A' C'
1344 F04
Figure 4. Typical V.10 Interface
A 51.5 S1 OFF S2 OFF LTC1344A Z 124 Z 51.5 B C IZ 3.25mA -10V -3V 3V - 3.25mA VZ 10V
1344 F05
V.10 RECEIVER
Figure 5. V.10 Interface Using the LTC1344A
V.11 (RS422) Termination A typical V.11 balanced interface is shown in Figure 6. A V.11 differential generator with outputs A and B with ground C is connected to a differential receiver with ground C', inputs A' connected to A, B' connected to B. The V.11 interface requires a differential termination at the receiver end that has a minimum value of 100. The receiver inputs must also be compliant with the impedance curve shown in Figure 7. In V.11 mode, switch S1 is turned on and S2 is turned off so the cable is terminated with a 103 impedance.
LTC1344A
APPLICATIONS INFORMATION
GENERATOR BALANCED INTERCONNECTING CABLE LOAD CABLE TERMINATION RECEIVER A A' 100 MIN
B C
B' C'
1344 F06
Figure 6. Typical V.11 Interface
A 51.5 S1 ON S2 OFF LTC1344A Z 124 Z 51.5 B C IZ 3.25mA -10V Z 3V - 3.25mA -3V VZ 10V
1344 F07
V.11 RECEIVER
Figure 7. V.11 Interface Using the LTC1344A
V.28 (RS232) Termination A typical V.28 unbalanced interface is shown in Figure 8. A V.28 single-ended generator output A with ground C is connected to a single-ended receiver with input A' connected to A, ground C' connected via the signal return ground to C. The V.28 standard requires a 5k terminating resistor to ground which is included in almost all compliant receivers as shown in Figure 9. Because the termination is included in the receiver, both switches S1 and S2 in the LTC1344A are turned off.
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GENERATOR
BALANCED INTERCONNECTING CABLE
LOAD CABLE TERMINATION RECEIVER
A C
A' C'
1344 F08
Figure 8. Typical V.28 Interface
A 51.5 S1 OFF S2 OFF LTC1344A V.28 RECEIVER
124
5k
51.5 B C
1344 F09
Figure 9. V.28 Interface Using the LTC1344A
V.35 Termination A typical V.35 balanced interface is shown in Figure 10. A V.35 differential generator with outputs A and B with ground C is connected to a differential receiver with ground C', inputs A' connected to A, B' connected to B. The V.35 interface requires a T-network termination at the receiver end and the generator end. In V.35 mode both switches S1 and S2 in the LTC1344A are turned on as shown in Figure 11. The differential impedance measured at the connector must be 100 10 and the impedance between shorted terminals A' and B' to ground C' must be 150 15. The input impedance of the V.35 receiver is connected in parallel with the T-network inside the LTC1344A, which could cause the overall impedance to fail the specification
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LTC1344A
APPLICATIONS INFORMATION
GENERATOR BALANCED INTERCONNECTING CABLE
A
LOAD CABLE TERMINATION RECEIVER
V.35 DRIVER
A 50 50 B C 125
A' 125 50 50 B' C'
1344 F10
Figure 10. Typical V.35 Interface
A 51.5 S1 ON S2 ON 51.5 B C IZ 1mA -7V Z 3V -0.8mA -3V VZ 12V
1344 F11
LTC1344A Z 124 Z
V.35 RECEIVER
Figure 11. V.35 Receiver Using the LTC1344A
if the receiver input impedance is on the low side. All of Linear Technology's V.35 receivers meet the RS485 input impedance specification as shown in Figure 11, which insures compliance with the V.35 specification when used with the LTC1344A.
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LTC1344A
51.5 S2 ON 51.5 B C1 100pF C
1344 F12
124
S1 ON
Figure 12. V.35 Driver Using the LTC1344A
The generator differential impedance must be 50 to 150 and the impedance between shorted terminals A and B to ground C must be 150 15. For the generator termination, switches S1 and S2 are both on and the top side of the center resistor is brought out to a pin so it can be bypassed with an external capacitor to reduce common mode noise as shown in Figure 12. Any mismatch in the driver rise and fall times or skew in the driver propagation delays will force current through the center termination resistor to ground causing a high frequency common mode spike on the A and B terminals. The common mode spike can cause EMI problems that are reduced by capacitor C1 which shunts much of the common mode energy to ground rather than down the cable. The LATCH Pin The LATCH pin (21) allows the select lines (M0, M1, M2 and DCE/DTE) to be shared with multiple LTC1344As, each with its own LATCH signal. When the LATCH pin is held low the select line input buffers are transparent. When the LATCH pin is pulled high, the select line input buffers latch the state of the Select pins so that changes on the select lines are ignored until LATCH is pulled low again. If the latch feature is not used, the LATCH pin should be tied to ground.
LTC1344A
TYPICAL APPLICATIONS N
Controller Selectable Multiprotocol DTE/DCE Port with DB-25 Connector
C6 C7 C8 100pF 100pF 100pF 3 VCC 5V 14 1 C3 1F 2 C1 1F 4 3 8 LTC1343 5 D1 D2 39 38 DTE_TXD/DCE_RXD 6 7 37 36 DTE_SCTE/DCE_RXC D3 35 34 9 10 12 13 D4 33 32 R1 31 30 R2 29 28 R3 27 26 DCE M2 M1 M0 EC 21 19 18 17 VCC 40 GND 24 DB-25 CONNECTOR VEE GND D1 28 27 26 3 25 24 D2 23 C11 1F 4 19 20 23 RTS A RTS B DTR A DTR B CTS A CTS B DSR A DSR B LB 23 C9, 1F VCC 1 VCC 2 VDD 1 15 12 17 9 3 16 25 7 CHARGE PUMP 44 43 42 41 C2 1F 2 C4 3.3F VEE 5467 9 10 C13 1F VCC LATCH 21 8 11 12 13 LTC1344A
DCE/DTE
M2
M1
C5 1F DTE_LL/DCE_TM
C12 1F
16 15 18 17 19 20 22 23 24 1 DTE LL A TXD A TXD B SCTE A SCTE B DCE TM A RXD A RXD B RXC A RXC B
M0
18 2 14 24 11
DTE_TXC/DCE_TXC
DTE_RXC/DCE_SCTE
14
DTE_RXD/DCE_TXD
15
DTE_TM/DCE_LL
16 20 22 11 25 R1 100k CTRL LATCH
R4
INVERT 423SET
LB
C10 1F DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
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5
D3 LTC1544 22 21 20 R2 19 18 R3 17 16 8 10 6 22 5 13 21
DTE_DCD/DCE_DCD DTE_DSR/DCE_DTR
6 7
R1
DTE_CTS/DCE_RTS
8 10 9 11 12 13 14 M0 M1 M2
DTE_RL/DCE_RL
R4 D4 INVERT
15
NC
DCE/DTE
DCE/DTE M2 M1 M0
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TXC A TXC B RXC A RXC B RXD A RXD B TM A SG SHIELD
TXC A TXC B SCTE A SCTE B TXD A TXD B LL A
DCD A DCD B DSR A DSR B CTS A CTS B RL A
DCD A DCD B DTR A DTR B RTS A RTS B RL A
1344A TA04
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LTC1344A
TYPICAL APPLICATIONS N
Cable Selectable Multiprotocol DTE/DCE Port with DB-25 Connector
C6 C7 C8 100pF 100pF 100pF
VCC 5V 14 3 C3 1F 1 C1 1F 2 4 C5 1F DTE_TXD/DCE_RXD DTE_SCTE/DCE_RXC 5 LTC1543 D1 D2 CHARGE PUMP 28 27 26 25 C4 3.3F C2 1F 2 VEE 5467 9 10 C13 1F VCC LATCH 21
DCE/DTE
M2
M1
C12 1F 24 23 22 21
16 15 18 17 19 20 22 23 24 1 VCC 2 14 24 11 DTE TXD A TXD B SCTE A SCTE B DCE RXD A RXD B RXC A RXC B
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7 8 9
D3 20 15 12 17 9 3 16 7 1 R1 TXC A TXC B RXC A RXC B RXD A RXD B SG SHIELD DB-25 CONNECTOR TXC A TXC B SCTE A SCTE B TXD A TXD B 19 18 R2 17 16 R3 M0 M1 M2 DCE/DTE 15
DTE_TXC/DCE_TXC
DTE_RXC/DCE_SCTE
DTE_RXD/DCE_TXD
10 11 12 NC 13 14
VCC C9, 1F 1 VCC 2 VDD 3 D1 VEE GND 28 27 26 25 24 D2 23 C11 1F
M0
25 DCE/DTE 21 M1 18 M0 4 RTS A 19 RTS B 20 DTR A 23 DTR B
C10 1F DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
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D3 LTC1544 22 21 20 R2 19 18 R3 17 16 CABLE WIRING FOR MODE SELECTION MODE V.35 RS449, V.36 RS232 15 NC PIN 18 PIN 7 NC PIN 7 PIN 21 PIN 7 PIN 7 NC CABLE WIRING FOR DTE/DCE SELECTION MODE PIN 25 DTE PIN 7 DCE NC 8 10 6 22 5 13
DTE_DCD/DCE_DCD DTE_DSR/DCE_DTR
6 7
R1
DTE_CTS/DCE_RTS
8 10 9 11 12 NC 13 14 M0 M1 M2
R4 D4
DCE/DTE INVERT
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11
12
13 LTC1344A
CTS A CTS B DSR A DSR B
DCD A DCD B DSR A DSR B CTS A CTS B
DCD A DCD B DTR A DTR B RTS A RTS B
1344A TA05
LTC1344A
PACKAGE DESCRIPTION
0.205 - 0.212** (5.20 - 5.38)
0.005 - 0.009 (0.13 - 0.22)
0.022 - 0.037 (0.55 - 0.95)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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Dimensions in inches (millimeters) unless otherwise noted.
G Package 24-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.318 - 0.328* (8.07 - 8.33) 24 23 22 21 20 19 18 17 16 15 14 13
0.301 - 0.311 (7.65 - 7.90)
1 2 3 4 5 6 7 8 9 10 11 12 0.068 - 0.078 (1.73 - 1.99)
0 - 8
0.0256 (0.65) BSC
0.010 - 0.015 (0.25 - 0.38)
0.002 - 0.008 (0.05 - 0.21)
G24 SSOP 0595
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LTC1344A
TYPICAL APPLICATIO
Figure 13 shows a typical application for the LTC1344A using the LTC1543 mixed mode transceiver chip to generate the clock and data signals for a serial interface. The LTC1344A VEE supply is generated from the LTC1543 charge pump and the select lines M0, M1, M2 and
M0 M1 M2
1 24 23
M0 M1 M2 LTC1344A
DCE/DTE
22 21
DCE/DTE LATCH VCC 14
C1 1F
LTC1543 11 M0 12 M1 13 M2 14 DCE/DTE 24 5 23 22 6 21 SCTE - RXC - TXD- SCTE + RXD- RXC+ DTE TXD+ DCE RXD+
7 20 8 19 18 9 17 16 10 15 TXC + TXC - RXC + RXC - RXD+ RXD- TXC + TXC - SCTE+ SCTE- TXD+ TXD-
1344 F13
RELATED PARTS
PART NUMBER LTC1334 LTC1343 LTC1345 LTC1346A LTC1543 LTC1544 DESCRIPTION Single Supply RS232/RS485 Transceiver Multiprotocol Serial Transceiver Single Supply V.35 Transceiver Dual Supply V.35 Transceiver Multiprotocol Serial Transceiver Multiprotocol Serial Transceiver COMMENTS 2 RS485 Dr/Rx or 4 RS232 Dr/Rx Pairs Software Selectable Mulitprotocol Interface 3 Dr/3 Rx for Data and CLK Signals 3 Dr/3 Rx for Data and CLK Signals Software-Selectable Transceiver for Data and CLK Signals Software-Selectable Transceiver for Control Signals
1344af, sn1344a LT/TP 0898 4K * PRINTED IN USA
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
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DCE/DTE are shared by both chips. Each driver output and receiver input is connected to one of the LTC1344A termination ports. Each electrical protocol can then be chosen using the digital select lines.
100pF 100pF 3 8 11 12 13 100pF VEE 2 26 C2 3.3F 5 4 6 7 9 10 16 15 18 17 19 20 4
Figure 13. Typical Application Using the LTC1344A
(c) LINEAR TECHNOLOGY CORPORATION 1998

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